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? semiconductor components industries, llc, 2008 november, 2008 ? rev. 11 1 publication order number: mc10ep139/d mc10ep139, mc100ep139 3.3v / 5v?ecl 2/4, 4/5/6 clock generation chip description the mc10/100ep139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the common enable (en ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. the internal enable flip ? flop is clocked on the falling edge of the input clock, ther efore, all associated specification limits are referenced to the negative edge of the clock input. upon start ? up, the internal flip ? flops will attain a random state; therefore the master reset (mr) input may require assertion to ensure system synchronization. internal di vider design ensures synchronization between the 2/4 and the 4/5/6 outputs within a device. all v cc and v ee pins must be externally connect ed to power supply to guarantee proper operation. the v bb pin, an internally generated voltage supply, is available to this device only. for single ? ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, vbb should be left open. the 100 series contains temperature compensation. features ? maximum frequency > 1.0 ghz typical ? 50 ps output ? to ? output skew ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ? 3.0 v to ? 5.5 v ? open input default state ? safety clamp on inputs ? synchronous enable/disable ? master reset for synchronization of multiple chips ? v bb output ? pb ? free packages are available marking diagrams* hep = mc10ep kep = mc100ep xxx = 10 or 100 a = assembly location l,wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package *for additional marking information, refer to application note and8002/d. tssop ? 20 dt suffix case 948e soic ? 20 dw suffix case 751d 1 http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 11 of this data sheet. ordering information 20 1 mcxxxep139 awlyywwg xxxx ep139 alyw 1 20 qfn ? 20 mn suffix case 485e hep or kep 139 alyw 1 (note: microdot may be in either location)
mc10ep139, mc100ep139 http://onsemi.com 2 clk figure 1. 20 ? lead pinout (top view) clk mr v cc q0 q1 q1 q2 q2 q3 q3 v ee en v cc q0 v bb warning: all v cc and v ee pins must be externally connected to a power supply to guarantee proper operation. divselb0 divselb1 divsela v cc mc10/100ep139 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 table 1. pin description pin function clk*, clk * ecl differential clock inputs en * ecl sync enable mr* ecl master reset v bb ecl reference output q0, q1, q0 , q1 ecl differential 2/4 outputs q2, q3, q2 , q3 ecl differential 4/5/6 outputs divsela* ecl frequency select input 2/4 divselb0* ecl frequency select input 4/5/6 divselb1 ecl frequency select input 4/5/6 v cc ecl positive supply v ee ecl negative supply ep exposed pad *pins will default low when left open. 1 2 3 4 5 15 14 13 12 11 678910 20 19 18 17 16 figure 2. qfn ? 20 pinout (top view) q0 q1 q1 v cc q0 v cc q2 q2 q3 q3 v ee clk clk mr en divselb0 v bb v cc divselb1 divsela exposed pad mc10/100ep139 warning: all v cc and v ee pins must be externally connected to a power supply to guarantee proper operation. the exposed pad (ep) on package bottom must be attached to a heat ? sinking conduit. the exposed pad may only be electrically connected to v ee .
mc10ep139, mc100ep139 http://onsemi.com 3 clk clk en mr divselb1 2/4 q0 q0 q1 q1 4/5/6 q2 q2 q3 q3 figure 3. logic diagram r r divsela divselb0 v ee table 2. function tables clk en mr function z zz x l h x l l h divide hold q0:3 reset q0:3 z = low ? to ? high transition zz = high ? to ? low transition divsela q0:1 outputs l h divide by 2 divide by 4 divselb0 divselb1 q2:3 outputs l h l h l l h h divide by 4 divide by 6 divide by 5 divide by 5 clk q ( 2) q ( 4) q ( 5) figure 4. clk and output timing diagram q ( 6) figure 5. timing diagram clk reset q ( n) t rr
mc10ep139, mc100ep139 http://onsemi.com 4 table 3. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb ? free pkg soic ? 20 tssop ? 20 qfn ? 20 level 1 level 1 n/a level 3 level 1 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 758 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ? 6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ? 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop ? 20 tssop ? 20 140 100 c/w c/w jc thermal resistance (junction ? to ? case) standard board tssop ? 20 23 to 41 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 20 soic ? 20 90 60 c/w c/w jc thermal resistance (junction ? to ? case) standard board soic ? 20 33 to 35 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm qfn ? 20 qfn ? 20 47 33 c/w c/w jc thermal resistance (junction ? to ? case) standard board qfn ? 20 18 c/w t sol wave solder pb pb ? free <2 to 3 sec @ 248 c <2 to 3 sec @ 260 c 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
mc10ep139, mc100ep139 http://onsemi.com 5 table 5. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 2) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 65 82 105 65 83 105 65 84 105 ma v oh output high voltage (note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (single ? ended) 2090 2415 2155 2480 2215 2540 mv v il input low voltage (single ? ended) 1365 1690 1460 1755 1490 1815 mv v bb output voltage reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mv v ihcmr input high voltage common mode range (differential configuration) (note 4) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ? 2.2 v. 3. all loading with 50 to v cc ? 2.0 v (see figure 10). 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 6. 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 5) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 65 82 105 65 83 105 65 84 105 ma v oh output high voltage (note 6) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (single ? ended) 3790 4115 3855 4180 3915 4240 mv v il input low voltage (single ? ended) 3065 3390 3130 3455 3190 3515 mv v bb output voltage reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mv v ihcmr input high voltage common mode range (differential configuration) (note 7) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to ? 0.5 v. 6. all loading with 50 to v cc ? 2.0 v (see figure 10). 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep139, mc100ep139 http://onsemi.com 6 table 7. 10ep dc characteristics, necl v cc = 0 v, v ee = ? 5.5 v to ? 3.0 v (note 8) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 65 82 105 65 83 105 65 84 105 ma v oh output high voltage (note 9) ? 1135 ? 1010 ? 885 ? 1070 ? 945 ? 820 ? 1010 ? 885 ? 760 mv v ol output low voltage (note 9) ? 1935 ? 1810 ? 1685 ? 1870 ? 1745 ? 1620 ? 1810 ? 1685 ? 1560 mv v ih input high voltage (single ? ended) ? 1210 ? 885 ? 1145 ? 820 ? 1085 ? 760 mv v il input low voltage (single ? ended) ? 1935 ? 1610 ? 1870 ? 1545 ? 1810 ? 1485 mv v bb output voltage reference ? 1510 ? 1410 ? 1310 ? 1445 ? 1345 ? 1245 ? 1385 ? 1285 ? 1185 mv v ihcmr input high voltage common mode range (differential configuration) (note 10) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. input and output parameters vary 1:1 with v cc . 9. all loading with 50 to v cc ? 2.0 v (see figure 10). 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 8. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 11) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 83 100 70 87 105 75 90 110 ma v oh output high voltage (note 12) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 12) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (single ? ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ? ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1725 1825 1925 1725 1825 1925 1725 1825 1925 mv v ihcmr input high voltage common mode range (differential configuration) (note 13) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ? 2.2 v. 12. all loading with 50 to v cc ? 2.0 v (see figure 10). 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep139, mc100ep139 http://onsemi.com 7 table 9. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 14) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 70 85 100 70 90 105 75 95 110 ma v oh output high voltage (note 15) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 15) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (single ? ended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (single ? ended) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3425 3525 3625 3425 3525 3625 3425 3525 3625 mv v ihcmr input high voltage common mode range (differential configuration) (note 16) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to ? 0.5 v. 15. all loading with 50 to v cc ? 2.0 v (see figure 10). 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 10. 100ep dc characteristics, necl v cc = 0 v, v ee = ? 5.5 v to ? 3.0 v (note 17) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 85 100 70 90 105 75 95 110 ma v oh output high voltage (note 18) ? 1145 ? 1020 ? 895 ? 1145 ? 1020 ? 895 ? 1145 ? 1020 ? 895 mv v ol output low voltage (note 18) ? 1945 ? 1820 ? 1695 ? 1945 ? 1820 ? 1695 ? 1945 ? 1820 ? 1695 mv v ih input high voltage (single ? ended) ? 1225 ? 880 ? 1225 ? 880 ? 1225 ? 880 mv v il input low voltage (single ? ended) ? 1945 ? 1625 ? 1945 ? 1625 ? 1945 ? 1625 mv v bb output voltage reference ? 1575 ? 1475 ? 1375 ? 1575 ? 1475 ? 1375 ? 1575 ? 1475 ? 1375 mv v ihcmr input high voltage common mode range (differential configuration) (note 19) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. input and output parameters vary 1:1 with v cc . 18. all loading with 50 to v cc ? 2.0 v (see figure 10). 19. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep139, mc100ep139 http://onsemi.com 8 table 11. ac characteristics v cc = 0 v; v ee = ? 3.0 v to ? 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 20) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figures 6, 7, 8 and 9 f max /jitter) > 1 > 1 > 1 ghz t plh , t phl propagation delay clk, q (diff) mr, q 550 700 700 800 800 900 600 700 750 850 900 1000 675 800 825 950 975 1100 ps t rr reset recovery 200 100 200 100 200 100 ps t s setup time en , clk divsel, clk 200 400 120 180 200 400 120 180 200 400 120 180 ps t h hold time clk , en clk, divsel 100 200 50 140 100 200 50 140 100 200 50 140 ps t pw minimum pulse width mr 550 450 550 450 550 450 ps t skew within device skew q, q device ? to ? device skew (note 21) 50 200 100 300 50 200 100 300 50 200 100 300 ps t jitter random clock jitter (rms) (see figures 6, 7, 8 and 9 f max /jitter) 0.2 < 1.0 0.2 < 1.0 0.2 < 1.5 ps v pp input voltage swing (differential con- figuration) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times q, q (20% ? 80%) 110 180 250 125 190 275 150 215 300 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v (see figure 10). 21. skew is measured between outputs under identical transitions. duty cycle skew is defined only for differential operation whe n the delays are measured from the cross point of the inputs to the cross point of the outputs.
mc10ep139, mc100ep139 http://onsemi.com 9 0 100 200 300 400 500 600 700 800 900 0 200 400 600 800 1000 1200 1400 1600 1800 2000 figure 6. 2, f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8 figure 7. 5, f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8
mc10ep139, mc100ep139 http://onsemi.com 10 0 100 200 300 400 500 600 700 800 900 0 200 400 600 800 1000 1200 1400 1600 1800 2000 figure 8. 4, f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8 figure 9. 6, f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8 figure 10. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v
mc10ep139, mc100ep139 http://onsemi.com 11 ordering information device package shipping ? mc10ep139dt tssop ? 20* 75 units / rail mc10ep139dtg tssop ? 20* 75 units / rail mc10ep139dtr2 tssop ? 20* 2500 / tape & reel mc10ep139dtr2g tssop ? 20* 2500 / tape & reel mc10ep139dw soic ? 20 38 units / rail mc10ep139dwg soic ? 20 (pb ? free 38 units / rail mc10ep139dwr2 soic ? 20 1000 / tape & reel mc10ep139dwr2g soic ? 20 (pb ? free 1000 / tape & reel mc10ep139mng qfn ? 20 (pb ? free) 92 units / rail mc10ep139mntxg qfn ? 20 (pb ? free) 3000 / tape & reel mc100ep139dt tssop ? 20* 75 units / rail mc100ep139dtg tssop ? 20* 75 units / rail mc100ep139dtr2 tssop ? 20* 2500 / tape & reel mc100ep139dtr2g tssop ? 20* 2500 / tape & reel mc100ep139dw soic ? 20 38 units / rail mc100ep139dwg soic ? 20 (pb ? free 38 units / rail mc100ep139dwr2 soic ? 20 1000 / tape & reel mc100ep139dwr2g soic ? 20 (pb ? free 1000 / tape & reel mc100ep139mng qfn ? 20 (pb ? free) 92 units / rail MC100EP139MNTXG qfn ? 20 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc10ep139, mc100ep139 http://onsemi.com 12 package dimensions tssop ? 20 case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mc10ep139, mc100ep139 http://onsemi.com 13 package dimensions soic ? 20 dw suffix plastic soic package case 751d ? 05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc10ep139, mc100ep139 http://onsemi.com 14 package dimensions x m 0.10 (0.004) t dim min max min max inches millimeters a 4.00 bsc 0.157 bsc b 4.00 bsc 0.157 bsc c 0.80 1.00 0.031 0.039 d 0.23 0.35 0.009 0.014 g 0.50 bsc 0.020 bsc h 1.38 1.43 0.054 0.056 j 0.20 ref 0.008 ref k 0.00 0.05 0.000 0.002 l 0.35 0.45 0.014 0.018 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension d applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ? t ? ? x ? note 3 seating plane l a m ? y ? b n 0.25 (0.010) t 0.25 (0.010) t j c k r 0.08 (0.003) t e h f p d y 1 5 6 15 11 20 16 e 2.75 2.85 0.108 0.112 f 2.75 2.85 0.108 0.112 m 2.00 bsc 0.079 bsc n 2.00 bsc 0.079 bsc p 1.38 1.43 0.054 0.056 r 0.60 0.80 0.024 0.031 g 10 qfn ? 20 case 485e ? 01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc10ep139/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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